Compare commits

...

2 Commits

Author SHA1 Message Date
Jonas Franz c7a0172a29
Remove debugging 4 years ago
Jonas Franz da149e94e1
Add random paging 4 years ago
  1. 36
      hal/paging.go
  2. 1
      programs/storage.hal

@ -1,7 +1,15 @@
package hal
import (
"fmt"
"math/rand"
"time"
)
const PageSize = 1024
var seed = rand.NewSource(time.Now().UnixNano())
var defaultRegister uint16 = 0
type Page struct {
@ -100,21 +108,15 @@ func (mmu *MMU) Write(address Address, content float64) {
//
func (mmu *MMU) Load(page *Page) {
if len(mmu.LoadedPages) >= 4 {
for index, loadedPage := range mmu.LoadedPages {
if loadedPage.Referenced {
loadedPage.Referenced = false
continue
}
mmu.movePageToDrive(loadedPage)
mmu.LoadedPages = append(mmu.LoadedPages[:index], mmu.LoadedPages[index+1:]...)
break
}
// Everything is referenced, we need to remove one
if len(mmu.LoadedPages) == 4 {
mmu.movePageToDrive(mmu.LoadedPages[3])
mmu.LoadedPages = mmu.LoadedPages[:3]
}
index := rand.New(seed).Intn(4)
removedPage := mmu.LoadedPages[index]
mmu.movePageToDrive(removedPage)
mmu.loadPageFromDrive(page)
mmu.LoadedPages[index] = page
return
}
mmu.loadPageFromDrive(page)
@ -127,7 +129,7 @@ func (mmu *MMU) findEmptyRegisterAddress() *uint16 {
for i = 0; i < uint16(len(mmu.module.register)/PageSize); i++ {
var isTaken bool
for _, loadedPage := range mmu.LoadedPages {
if *loadedPage.RegisterAddress == i {
if loadedPage.RegisterAddress != nil && *loadedPage.RegisterAddress == i {
isTaken = true
break
}
@ -142,7 +144,9 @@ func (mmu *MMU) findEmptyRegisterAddress() *uint16 {
}
func (mmu *MMU) movePageToDrive(page *Page) {
if page.RegisterAddress == nil {
fmt.Printf("PAGE NOT IN MEMORY\n")
}
for i := 0; i < PageSize-1; i++ {
mmu.drive[page.PageNumber][i] = mmu.module.register[i+page.RegisterOffset()]
}

@ -15,7 +15,6 @@
0009 MULNUM 2
0010 ADDNUM 1
0011 STORE 1
0012 OUT 1
0013 SUB 2
0014 JUMPNEG 0006

Loading…
Cancel
Save